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"The area customers most want improvement in is energy efficiency," Zhang said. "This is true across the board, whether you are the edge guy, smartphone, mobile, IoT application, or high-performance AI data centre." As the manufacturer behind AI chips for Nvidia and AMD, plus custom processors for Google, Amazon, Meta, and Microsoft, TSMC has a uniquely broad view of what its customers are demanding.
The company expects its chips to cut power consumption by up to 30% between its current N2 technology and its A14 generation, due around 2028, while delivering more than 20% higher computing performance.
TSMC also signalled its priorities in April when it said it would delay adoption of ASML's next-generation extreme ultraviolet lithography technology for several years. That decision underscores how design features that improve energy efficiency have become more urgent than simply shrinking circuitry for the coming generation of AI chips.
TSMC Says Energy Efficiency, Not Raw Power, Now Drives AI Chip Design
May 29, 2026
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The world's largest contract chipmaker says surging electricity demand from AI is making energy efficiency the primary force shaping future chip development. A senior TSMC executive says customers across every sector now want performance gains that don't increase power draw.
A Turning Point for Chipmaking
The most important number in artificial intelligence may no longer be how fast a chip can compute, but how much power it burns doing so. Speaking at a conference in Amsterdam, Kevin Zhang, Senior Vice President of Business Development at TSMC, told reporters that energy efficiency, rather than raw computing power, has become the primary constraint shaping the future of chip design."The area customers most want improvement in is energy efficiency," Zhang said. "This is true across the board, whether you are the edge guy, smartphone, mobile, IoT application, or high-performance AI data centre." As the manufacturer behind AI chips for Nvidia and AMD, plus custom processors for Google, Amazon, Meta, and Microsoft, TSMC has a uniquely broad view of what its customers are demanding.
Beyond Transistor Density
For decades, progress in computing has meant cramming more transistors onto each chip. That playbook is no longer enough on its own to sustain performance for power-hungry AI workloads. Zhang said transistor density improvements remain central to TSMC's roadmap, but other techniques are becoming increasingly important, including advanced packaging, chip stacking, and photonics, which moves data using light rather than electrical signals.The company expects its chips to cut power consumption by up to 30% between its current N2 technology and its A14 generation, due around 2028, while delivering more than 20% higher computing performance.
A Competitive Landscape Shifting Fast
The comments arrive as rivals chase alternative paths to improvement. Chinese competitor Huawei this week unveiled its "Tau Scaling Law" plan to boost performance by speeding up how data moves within chips, an approach Zhang said depends heavily on integrating components more tightly through methods like 3D stacking.TSMC also signalled its priorities in April when it said it would delay adoption of ASML's next-generation extreme ultraviolet lithography technology for several years. That decision underscores how design features that improve energy efficiency have become more urgent than simply shrinking circuitry for the coming generation of AI chips.
Why It Matters
The shift reframes how the entire industry measures progress. As data centres expand to feed the AI boom, electricity has become a hard limit on how much computing the world can actually deploy. By making efficiency the headline metric, TSMC is acknowledging that the future of AI will be decided as much by the power grid as by the laboratory.Published May 29, 2026 at 2:10pm